1. Field of the Invention
The present invention relates to an output driver circuit for outputting differential signals.
2. Description of the Related Art
Several intra-panel interface bus standards between the panel timing controller (T-con) and the column drivers, such as RSDS (reduced swing differential signaling), mini-ENDS (mini-low voltage differential signaling), PPDS (point to point differential signaling), are defined and used widely.
In the interface bus standards, depending on an application, specifications of an output amplitude voltage Vod and an output common mode voltage Voc of differential output signals are defined. As illustrated in FIG. 3, the output amplitude voltage Vod is a differential voltage (|Vod|=|VOH|−|VOL|) between a high-level voltage VON and a low-level voltage VOL of differential output signals. The output common mode voltage Voc is a midpoint voltage (Voc=(VOH+VOL)/2) of the high-level voltage VOH and the low-level voltage VOL of the differential output signals.
Accordingly, it is desirable to maintain the output amplitude voltage Vod and the output common mode voltage Voc. Methods for controlling the output amplitude voltage Vod and the output common mode voltage Voc are important for obtaining a stable output. For example, the following methods have been proposed: a method to use a common feedback on each driver circuit, and a method to use in common a replica circuit by a plurality of driver circuits.
In the common feedback method, within each driver circuit, two serially connected resistors are provided between output nodes of differential signals in the individual driver circuit. Using an operational amplifier, a transistor that determines an output common mode voltage Voc of an output driver circuit is controlled such that an externally supplied reference voltage is equal to a voltage, the output common mode voltage Voc in the driver circuit, of a node at a midpoint of the two resistors.
Meanwhile, in the replica circuit method, an operational amplifier, and a replica circuit, which is an equivalent circuit of a driver circuit to which an external termination resistor is connected, are commonly used by a plurality of driver circuits. Using the operational amplifier, a transistor that determines an output common mode voltage Voc of the driver circuit is controlled such that an externally supplied reference voltage is equal to a voltage, the output common mode voltage Voc of the driver circuit, of a node at a midpoint of two resistors. These two resistors have a resistance value that is half of the termination resistor and are serially connected to nodes in the replica circuit. The nodes correspond to output nodes of differential signals in the driver circuit.
Hereinafter, a conventional output driver circuit that employs the replica circuit method is described.
FIG. 4 is a view illustrating an example of a conventional output driver circuit. The output driver circuit 40 illustrated in FIG. 4 has been proposed in Japanese Patent No. JP-B-3967321. The output driver circuit 40 includes a driver circuit 12 at an output final stage, a replica circuit 14, and an operational amplifier 16.
The driver circuit 12 includes N type MOS transistors (hereinafter, referred to as NMOS) 18, 20, 22, 24, 26, and 28. The NMOS 18 controls an output common mode voltage Voc. The NMOS 20 controls a current ID flowing in the driver circuit 12. The four NMOSs 22, 24, 26, and 28 perform switching in response to differential input signals In1 and In2 supplied from a circuit (for example, predriver circuit) in a preceding stage to supply differential output signals to both ends of an external termination resistor 29.
In the driver circuit 12, for example, in a case where the differential input signals In1 and In2 are at a high level and at a low level, respectively, the NMOS 22 and NMOS 28 are ON-state, and the NMOS 24 and NMOS 26 are OFF-state. Then, the current ID flows from a power supply VDD to a ground VSS via the NMOS 18, the NMOS 22, the termination resistor 29, the NMOS 28, and the NMOS 20. On the other hand, in a case where the differential input signals In1 and In2 are at a low level and at a high level, respectively, the current flows in a state opposite to the above.
The replica circuit 14 includes an NMOS 30 corresponding to the NMOS 18 in the driver circuit 12, a NMOS 32 corresponding to the NMOS 22 or the NMOS 26 in an ON-state, two serially connected resistors 37a and 37b corresponding to the termination resistor 29, an NMOS 34 corresponding to the NMOS 24 or the NMOS 28 in an ON-state, and an NMOS 36 corresponding to the NMOS 20.
A size of each NMOS that forms the replica circuit 14 is 1/n times (n is a positive integer) of a size of the corresponding NMOS that forms the driver circuit 12. Each of the two resistors 37a and 37b has a resistance value nRT/2 that is n/2 times a resistance value RT of the termination resistor 29.
An externally supplied reference voltage VREF2 is commonly input to a gate of the NMOS 36 in the replica circuit 14 and a gate of the NMOS 20 in the driver circuit 12 so as to form a current mirror circuit. As described above, since the NMOS 36 and the NMOS 20 form the current mirror circuit, in the replica circuit 14, a current ID/n that is 1/n times of the current ID flowing in the driver circuit 12 flows through the NMOS 36.
An externally supplied reference voltage VREF1 is input to a positive input terminal in the operational amplifier 16. A voltage of a node at a midpoint of the two resistors 37a and 37b in the replica circuit 14 is fed back to a negative input terminal of the operational amplifier 16. By this configuration, the NMOS 30 is controlled by the operational amplifier 16 such that the voltage of the node at the midpoint of the two resistors 37a and 37b in the replica circuit 14 is equal to the reference voltage VREF1.
An output signal of the operational amplifier 16 is commonly supplied to a gate of the NMOS 30 in the replica circuit 14 and a gate of the NMOS 18 in the driver circuit 12. Accordingly, the voltage of the node at the midpoint of the two resistors 37a and 37b in the replica circuit 14 varies simultaneously with the output common mode voltage Voc of the differential output signals supplied from the driver circuit 12 to both ends of the termination resistor 29. As a result, and the voltage Voc is controlled to be a voltage equal to the reference voltage VREF1.
An output amplitude voltage Vod of the differential output signals supplied from the driver circuit 12 to the both ends of the termination resistor 29 is determined by a product of the resistance value RT of the termination resistor 29 and the current ID flowing in the driver circuit 12 in accordance with the reference voltage VREF2 (Vod=RT×ID).
However, the resistance value nRT/2 of the two resistors 37a and 37b in the replica circuit 14 embedded in an LSI circuit vary within a range of ±20%, under the influence of manufacturing process variation. The variation is larger than the variation of the resistance value RT of the external termination resistor 29, which is normally within a range of several percent.
Accordingly, even if the feedback control accurately maintains the voltage of the node at the midpoint of the two resistors 37a and 37b equal to the reference voltage VREF1, the output common mode voltage Voc of the differential signals output from the output driver circuit 40 varies by a mismatch between the resistance values nRT/2 of the built-in resistors 37a and 37b and the resistance value RT of the external termination resistor 29.